COMP 222 Quiz 1: Numbers, Memory & Registers

CSUN COMP222-16.. Quizzes > Quiz 1: Number... Spring 2023 Quiz 1: Numbers, Memory & Registers Account Home Due Feb 6 at 11:59pm Points 15 Questions 15 Announcements Dashboard Available Jan 30 at 12am - Feb 6 at 11:59pm Time Limit None Assignments Discussions Courses Instructions Grades 1 due by Monday at midnight. Calendar People Pages Inbox Attempt History Files Attempt Time Score Syllabus History KEPT Attempt 2 4 minutes 15 out of 15 Quizzes LATEST Attempt 2 4 minutes 15 out of 15 ? Studio BigBlueButton Attempt 1 389 minutes 14 out of 15 Collaborations Help & Chat Correct answers will be available Feb 7 at 1am - May 16 at 12am. Follett Discover Score for this quiz: 15 out of 15 Submitted Feb 6 at 4:54pm This attempt took 4 minutes. Question 1 1/1 pts CPU's with a 16-bit address can directly address how much memory: 4 GiB 64 GB 64 KiB 16 KB Question 2 1/1 pts CPU's with a 32-bit address can directly address how much memory: 4 GiB 3200 KB 1 GB 2 MB

Question 3 1/1 pts 210 exactly - in hexadecimal: 0x0400 Ox100 0x0210 0x1000 Question 4 1/1 pts "Hell" is stored in memory in Little Endian (MIPS default) as: Hell (ASCII) lleH (ASCII) 0x6c6c6a4a 0xff6c496c Question 5 1/1 pts Static data is stored in which memory segment: heap text stack data

Question 6 1/1 pts Dynamic data is stored in which memory segment: text heap stack data Question 7 1/1 pts I/O is addressed in which memory segment: stack MMIO heap 10 Question 8 1/1 pts In a General Register CPU, R-format instructions address how many registers: 1 0 3 2

Question 9 1/1 pts In any CPU, which register holds a pointer to the top of the stack: PC SP GP FP Question 10 1/1 pts At the Macro architecture level, we address all of which units: GPU's MLM Cores and caches CPU cores Question 11 1/1 pts At the Micro architecture level, we address which functions: Branch prediction Cores Registers ALU's

Question 10 1/ 1 pts At the Macro architecture level, we address all of which units: GPU's MLM Cores and caches CPU cores Question 11 1/ 1 pts At the Micro architecture level, we address which functions: Branch prediction Cores Registers ALU's Question 12 1/ 1 pts Which is NOT a defined level of Computer Architecture in the stack model: Micro-architecture Shared L2 cache Macro-architecture ISA

Question 13 1/ 1 pts A MIPS CPU architecture provides for a main integer processor. plus: Up to 4 GPU's Up to 4 co-processors, including an FPU Up to 4 Program Counters Dedicated registers Question 14 1/1 pts The C. V. N. Z flags are all always updated by which one of these instructions: ori for and add Question 15 1/1 pts The "Program Counter" is stored in which Registers in MIPS, ARMv5: $0, R15 $15. R14 PC, R15 $sp. RO Quiz Score: 15 out of 15